A conventional ECL/CML to TTL translator circuit 10, coupled between an ECL/CML gate 12 and a TTL gate 14 is illustrated in FIG. 1. The ECL gate 12 provides the input to the translator section 10 and the ECL gate voltage levels are referenced to the higher reference voltage level positive power rail V.sub.CC (ECL) The translator section 10 in turn provides the input to drive the TTL gate 14. The TTL gate voltage levels are referenced to the lower reference voltage level ground power rail GND (TTL). The ECL gate 12 includes ECL input transistors Q1 and Q2 with emitter nodes tied together to the ECL tail current source transistor element Q3 and tail resistor R3. Current source transistor element Q3 is provided with base drive current by tail current source voltage V.sub.CS and sources tail current through tail resistor R3 to a low voltage level V.sub.EE which in this example may be ground potential GND. The ECL input transistors Q1 and Q2 provide alternative collector lead resistor current paths through swing resistors R1 and R2. Complementary high and low logic base current levels at the complementary inputs I.sub.IN (1) and I.sub.IN (0) at the respective base nodes of the input transistors Q1 and Q2 determine which transistor is conducting for conducting tail current generated by current source transistor element Q3 through the respective swing resistor.
The complementary outputs of ECL gate 12 are taken from the respective collector nodes of ECL input transistors Q1 and Q2. The voltage swing between the logic high and low level output signals is established by the magnitude of the tail current generated by current source transistor element Q3 and tail resistor R3, and by the swing resistors R1 and R2 which are generally of equal value. The complementary output signals are delivered through emitter follower output buffer transistor elements Q1A and Q2A respectively.
In the conventional translator circuit 10 of FIG. 1, the emitter follower output transistor elements Q1A and Q2A are coupled in respective branch circuits 15,16 of a current mirror circuit. The current mirror circuit is established by current mirror transistor elements Q4 and Q5 coupled in current mirror configuration with respective collector lead resistors R4 and R5. Transistor element Q4 is a base collector shorted (BCS) transistor. Resistors R4 and R5 are of equal value and resistor R4 establishes the current level in the branch circuit 15 which is mirrored in branch circuit 16.
The current flowing in branch circuit 15 is established by resistor R4 and the voltage drop across resistor R4 which is dependent upon V.sub.CC. Analysis reveals that resistor R5 in branch circuit 16 shifts the reference voltage level of the output signal on line 16 from V.sub.CC to ground potential at the collector node of the second current mirror transistor Q5. This is because the V.sub.CC dependency of the voltage drop across resistor R5 is cancelled by the V.sub.CC dependency of the current mirrored in branch circuit 16 from branch circuit 15. With the V.sub.CC dependencies offsetting and cancelling each other in branch circuit 16, the voltage level at the collector node of current mirror transistor Q5 is set with reference to the TTL ground potential level GND (TTL).
The reference voltage level shifted output signal from the collector node of current mirror transistor Q5 is coupled directly to the base node of inverting stage transistor Q6 which in turn controls the phase splitter transistor element Q9 of the TTL gate 14. While the current mirror transistor element Q5 in current mirror branch circuit 16 operates in the linear or non-saturation operating region characteristic of the emitter coupled logic, the inverting stage transistor element Q6 operates in the non-linear saturation operating region characteristic of the TTL gate transistor elements. The reference voltage level shifted output signal directly drives the first stage transistor element associated with the TTL gate and operating in the non-linear saturation region. The dividing line between components operating in the linear non-saturation operating region characteristic of the emitter coupled logic, and the components operating in the non-linear saturation operating region characteristic of the transistor transistor logic is indicated by dash line 18.
The first stage saturation region transistor element Q6 is coupled to the base of phase splitter transistor element Q9 of the TTL gate 14 through diode D1 and includes collector lead resistors R6 and R16. The collector node of inverting stage saturation region transistor element Q6 is coupled through the boot strap circuit provided by boot strap transistor element Q7 and resistor R7 to the base node of transistor element Q6 and to the reference voltage level shifted collector node of current mirror transistor element Q5. The boot strap current applied through resistor R7 after the base of first stage TTL transistor element Q6 is discharged, assures that current mirror transistor element Q5 remains out of the saturation operating region and in the linear operating region.
A disadvantage of the conventional translator circuit 10 of FIG. 1 is that the current mirror circuit is a switching current mirror circuit. The current mirror transistor elements Q4 and Q5 switch between two different emitter current densities in response to switching between high and low logic levels at the collector node of ECL input transistor Q1 and switching of the emitter current from emitter follower buffer transistor element Q1A. The switching of emitter current densities by current mirror transistor Q4 is mirrored by current mirror transistor Q5. The current mirror current source transistor elements Q4 and Q5 can respond only slowly with delayed switching of the voltage level at the collector node of current mirror transistor element Q5. In this conventional translator circuit the current mirror branch circuits 15 and 16 operate together switching between two different current level states with two different voltage drops across resistors R4 and R5 according to the high or low switching level at the input of ECL input transistor Q1. Because of the slow switching response of current source transistors Q4 and Q5, inherent propagation delays are introduced in the translator section 10.
Furthermore, discharge of the base of the first saturation stage transistor element Q6 takes place directly through the current mirror transistor element Q5. The switching from high to low voltage level at the collector node of current mirror transistor element Q5, and discharge of the base of transistor element Q6 operating in the saturation region, follows a delayed linear ramp function as shown for example in FIG. 1A. Overall, the same level switching node, that is, the collector node of transistor element Q5 where the reference voltage level shift occurs also drives the base of the first stage transistor element Q6 operating in the TTL saturation operating region. The same transistor element component Q5 must perform these simultaneous functions.
Thus, according to the prior art ECL/CML to TTL translator circuit 10 the reference voltage level shift and the operating region translation take place in the same branch circuit 16 of a switching current mirror circuit. The same current mirror current source transistor element Q5 drives both the reference voltage level shift and drains the base of the first TTL saturation operating region transistor element. The result is delayed propagation during switching transitions and in particular high to low transitions at the ECL gate input and TTL gate output. The same component, a current source current mirror transistor element Q5 with the inherently slow switching function as illustrated in FIG. 1A drives both functions of reference voltage level shifting and operating region translation limiting the switching speed of the translator circuit.
The TTL gate 14 is provided by the conventional components including the Darlington pair of pullup transistor elements Q11 and Q12 for sourcing current from the high potential power supply rail V.sub.CC (TTL) to the output V.sub.OUT (TTL). Pulldown transistor element Q13 sinks current from the output V.sub.OUT (TTL) to the lower ground potential rail GND (TTL). Resistor R12 and diode D12 provide resistive pulldown discharge for the base of pulldown transistor element Q13. An "A. C. Miller killer" of the type described in U.S. Pat. No. 4,321,490, for active discharge of capacitive feedback Miller current at the base of pulldown transistor element Q13 is provided by active discharge transistor Q14 and associated diode network D9, D10, and D11. Accelerated switching of the output from high to low potential is provided by feedback transistor Q10 with feedback transistor base drive through resistor R10 and diode D6. Speed up diode D5 accelerates turnoff at the base of Darlington transistor Q12 during transition from high to low potential at the output V.sub.OUT (TTL). Additional bias components associated with the Darlington pullup transistor elements Q11 and Q12 include resistor R11, diode D7 and diode D8.